Thin film transistors, as switching elements or integrated elements of peripheral driving circuits, are important elements in panel display technology. The exhibition of the panel display is directly dependent on the performance of the thin film transistors. Thin film transistors generally comprise single-gate transistors and dual-gate transistors. A dual-gate transistor in contrast to a single-gate transistor has advantage such as a high drive capability, a steep subthreshold slope, and a small circuit area. Combination of dual-gate transistors can be reasonably used to implement devices and circuits with new functions. However, the process for manufacturing dual-gate thin film transistors, especially planar dual-gate thin film transistors, is complicated. In particular, it is difficult to realize self-aligning in dual-gate thin film transistors. Conventional methods are those for manufacturing non-self-aligned. Non-self-aligning will cause the device to have a large performance dispersion and result in a large parasitic element such as a large parasitic capacitance, which is unacceptable to a panel display application. Thus, there is a need implement a method for manufacturing self-aligned dual-gate thin film transistors.